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Verilog

Verilog - Hardware description language

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Verilog is a hardware description language created in 1984.

#58on PLDB 39Years Old 48kRepos

Try now: Riju

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.. Read more on Wikipedia...


Example from Riju:
module main; initial begin $display("Hello, world!"); end endmodule
Example from hello-world:
module main; initial begin $display("Hello World"); $finish; end endmodule
/* Hello World in Verilog. */ module main; initial begin $display("Hello, World"); $finish ; end endmodule
Example from Linguist:
`timescale 1ns / 1ps // Copyright (C) 2008 Schuyler Eldridge, Boston University // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation, either version 3 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. module mux(opA,opB,sum,dsp_sel,out); input [3:0] opA,opB; input [4:0] sum; input [1:0] dsp_sel; output [3:0] out; reg cout; always @ (sum) begin if (sum[4] == 1) cout <= 4'b0001; else cout <= 4'b0000; end reg out; always @(dsp_sel,sum,cout,opB,opA) begin if (dsp_sel == 2'b00) out <= sum[3:0]; else if (dsp_sel == 2'b01) out <= cout; else if (dsp_sel == 2'b10) out <= opB; else if (dsp_sel == 2'b11) out <= opA; end endmodule
Example from Wikipedia:
initial a = 0; initial b = a; initial begin #1; $display("Value a=%d Value of b=%d",a,b); end
Verilog Keywords
always assign automatic begin case casex casez cell config deassign default defparam design disable edge else end endcase endconfig endfunction endgenerate endmodule endprimitive endspecify endtable endtask event for force forever fork function generate genvar if ifnone incdir include initial inout input instance join liblist library localparam macromodule module negedge noshowcancelled output parameter posedge primitive pulsestyle_ondetect pulsestyle_onevent reg release repeat scalared showcancelled signed specify specparam strength table task tri tri0 tri1 triand wand trior wor trireg unsigned use vectored wait while wire

Language features

Feature Supported Token Example
Binary Literals
// ([0-9]+)|(\'b)[01]+
Integers
// ([0-9]+)|(\'d)[0-9]+
Floats
// (\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?
Hexadecimals
// ([0-9]+)|(\'h)[0-9a-fA-F]+
Octals
// ([0-9]+)|(\'o)[0-7]+
Conditionals
Functions
While Loops
Case Sensitivity
Strings "
"Hello world"
MultiLine Comments /* */
/* A comment
*/
Print() Debugging $display
Line Comments //
// A comment
Comments
Semantic Indentation X

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