SystemVerilog

SystemVerilog is a programming language created in 2002.

#238on PLDB

22Years Old

10kRepos

SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.. Read more on Wikipedia...

SystemVerilog Wikipedia page
SystemVerilog docs
There are at least 9,972 SystemVerilog repos on GitHub
SystemVerilog first developed in Synopsys
file extensions for SystemVerilog include sv, svh, vh, header and file
The Google BigQuery Public Dataset GitHub snapshot shows 872 users using SystemVerilog in 1k repos on GitHub
Explore SystemVerilog snippets on Rosetta Code
Monaco package for syntax highlighting SystemVerilog
Pygments supports syntax highlighting for SystemVerilog
GitHub supports syntax highlighting for SystemVerilog
See also: (7 related languages)Verilog, VHDL, OpenVera, Java, C, Property Specification Language, AXIOM

Example from Linguist:

function integer log2;
  input integer x;
  begin
    x = x-1;
    for (log2 = 0; x > 0; log2 = log2 + 1)
      x = x >> 1;
  end
endfunction

Example from Wikipedia:

class eth_frame;
   // Definitions as above
   covergroup cov;
      coverpoint dest {
          bins bcast[1] = {48'hFFFFFFFFFFFF};
          bins ucast[1] = default;
      }
      coverpoint f_type {
          bins length[16] = { [0:1535] };
          bins typed[16] = { [1536:32767] };
          bins other[1] = default;
      }
      psize: coverpoint payload.size {
          bins size[] = { 46, [47:63], 64, [65:511], [512:1023], [1024:1499], 1500 };
      }

      sz_x_t: cross f_type, psize;
   endgroup
endclass

SystemVerilog Keywords

accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case casex casez cell chandle checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event eventually expect export extends extern final first_match for force foreach forever fork forkjoin function generate genvar global highz0 highz1 if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inout input inside instance int integer interconnect interface intersect join join_any join_none large let liblist library local localparam logic longint macromodule matches medium modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or output package packed parameter pmos posedge primitive priority program property protected pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos real realtime ref reg reject_on release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared sequence shortint shortreal showcancelled signed small soft solve specify specparam static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on sync_reject_on table tagged task this throughout time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 unsigned until until_with untyped use uwire var vectored virtual void wait wait_order wand weak weak0 weak1 while wildcard wire with within wor xnor xor

Feature	Supported	Token	Example
Binary Literals	✓		// ([1-9][_0-9])?\s\'[sS]?[bB]\s[xXzZ?01][_xXzZ?01]
Integers	✓		// ([1-9][_0-9])?\s\'[sS]?[dD]\s[xXzZ?0-9][_xXzZ?0-9]
Floats	✓		// (\d+\.\d*\|\.\d+\|\d+)[eE][+-]?\d+[lL]?
Hexadecimals	✓		// ([1-9][_0-9])?\s\'[sS]?[hH]\s[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]
Octals	✓		// ([1-9][_0-9])?\s\'[sS]?[oO]\s[xXzZ?0-7][_xXzZ?0-7]
Conditionals	✓
Inheritance	✓
Functions	✓
Constants	✓
Classes	✓
While Loops	✓
MultiLine Comments	✓	/* */	/* A comment */
Strings	✓
Comments	✓		// A comment
Line Comments	✓	//	// A comment
Semantic Indentation	X

SystemVerilog - Programming language

Language features